Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test (DUT). It is command-line based with an optional Tcl/Tk GUI report viewer, making it portable across almost all platforms.

Covered is a tool that uses your design files along with standard VCD or LXT dump files to analyze the code coverage of the DUT. The code coverage information is stored in a special database file that can be retrieved and "merged" with new coverage information to create a summed coverage total for several tests. After a database file has been created, the user may generate various ASCII reports that summarize the coverage information or run Covered's GUI to interactively analyze the coverage information.